1. Field of the Invention
The present invention relates to a semiconductor memory, more particularly, to an address signal generator in a semiconductor memory which is capable of generating address signals with a high speed.
2. Discussion of Related Art
When a read or a write operation is controlled by a CPU in a semiconductor memory, there exists a timing margin, i.e., so-called set-up time and holding time, for performing synchronization with a clock. The set-up time is a time for confirming a data before the generation of a control signal. The holding time is a time during which the confirmed data maintains its state after the generation of the control signal.
FIG. 1 shows a circuit for an address signal generator in a semiconductor memory according to a related art.
Referring to FIG. 1, an address signal generator consists of NOR gates 108 and 112 and inverters 110 and 114. In the address signal generator, an external address BXIN is transformed into address signals BXT and BXB. The external address BXIN is inputted to an inverter 102. Then, the address BXIN is latched by a latch consisting of inverters 104 and 106. An output of the inverter 102 is inputted to the NOR gate 112. An output of the latch, i.e., the output of the inverter 104, is inputted to the other NOR gate 108. The inverter 102 and the inverter 106 of the latch are tri-state inverters which are enabled by an address enabling signal XAEI and its inverted signal.
The inverter 102 is enabled provided that the address enabling signal XAEI is at a low level. The inverter 106 of the latch is enabled when the address enabling signal XAEI is at a high level, thereby latching the external address BXIN inputted through the inverter 102. Namely, during a period defined by the address enabling signal XAEI, the inputting and the latching operations of the external address BXIN are completed.
An inverted signal of the address enabling signal XAEI enables the inverter 106 of the latch as soon as it is inputted to the NOR gates 108 and 112 which actually generate an address. Thus, the output of an inverter 116 should be at a low level so that the outputs of the inverter 102 and the inverter 104 of the latch are outputted as the address signals BXT and BXB. Namely, the output of the inverter 116 which is an inverted signal of the address enabling signal XAEI enables the address signal generator as well.
Therefore, the outputs of the inverters 102 and 104 are outputted as the address signals BXB and BXT respectively while the output of the inverter 116 is at a low level (which means that the address enabling signal XAEI is at a high level).
FIG. 2 is a timing diagram showing operational characteristics of an address signal generator in a semiconductor memory according to a related art. In FIG. 2, t1 is a set-up time. Referring to FIG. 2, an external address BXIN is first generated. Thereafter, address signals BXT and BXB are generated after a time interval t3 following the time point at which an address enabling signal XAEI goes up to a high level.
Namely, the external address BXIN has been confirmed at first. After a predetermined time t1, the address enabling signal XAEI goes up to a high level. After the address enabling signal XAEI has gone to the high level, the logic value is maintained for a predetermined time t2. In this case, t1 and t2 represent the so-called set-up time and holding time, respectively.
The logic values of the address signals BXT and BXB are complementary to each other. BXT and BXB are at low and high levels respectively provided that the external address BXIN is at a low level. Otherwise, BXT and BXB are at high and low levels respectively provided that the external address BXIN is at a high level.
Once the address enabling signal XAEI goes to a low level, the address signals BXT and BXB are fixed to a high level regardless of the logic value of the external address BXIN.
As shown in FIG. 2, the address signals BXT and BXB are generated after a time of t3 from a time point at which the address enabling signal XAEI has gone up to a high level. This is because it takes some time for the outputs of the NOR gates 108 and 112 in FIG. 1 to be enabled by the address enabling signal XAEI.
FIG. 3 shows a circuit for generating an address enabling signal XAEI in a semiconductor memory according to a related art.
Referring to FIG. 3, four buffers 302a to 302d are connected in series and are used as delaying means which decide the value of ti (i.e., t1 through t3 shown in FIG. 2) by sizes of the delaying means. Namely, the size of ti is controlled by manipulating the sizes of the buffers 302a to 302d.
A bank selection signal BANKi is inputted to the first buffer 302a and is enabled by a chip enabling signal ACT. An output of the fourth buffer 302d is the address enabling signal XAEI. The output of the buffer 302d may be outputted as a sense amplifier enabling signal SAE and a word line enabling signal WLE through other buffers 304, 306 and 308.
As mentioned in the above description, the delay of generating the address signals BXT and BXB by the address enabling signal XAEI hinders high-speed signals required for a high-speed system, memory devices, etc.